Stacking up // EIT Digital

Stacking up

A four-layer prototype high-rise chip built by Stanford engineers. The bottom and top layers are logic transistors. Sandwiched between them are two layers of memory. The vertical tubes are nanoscale electronic “elevators” that connect logic and memory, allowing them to work together efficiently. Credit: Max Shulaker, Stanford

Moore's law end is in sight (at least in its classic prediction on silicon) but still researchers are looking around for ways to improve chips performances thus postponing its demise.

One of the roadblock in the increasing of performances is that density of transistors on a chip would require smaller individual transistors (and we have reached the 10nm scale) but transistors size cannot be decreased much further without getting in the way of quantum effects (and in some cases we already hit that thresholds), nor frequency can be increased much further since we would hit a heat barrier, a point where the chip will melt down.

However, density so far has been played in 2 dimensions with very limited results in the third dimension, that is stacking transistors on the plane and in the volume. The main issue in stacking transistors "vertically" (in volume) is how to interconnect them. As you get more and more transistors the interconnections grow exponentially and is (already) taking most of the space in the chip (that is not very different from our brain where axons and dendrites make most of the brain mass).

This is what researchers at Stanford think they have solved: creating a stacked architecture that can support dense interconnectivity. 

They are proposing a four layers stack, with processing taking place in the other layers (top and bottom), also nice in terms of heat dissipation since processing uses more power than storage, and the two middle layer serving as memory.

The interconnection is made with CNT (Carbon Nano Tubes) and the key innovation here is how to industrially manufacture the CNT interconnections. Their work has been presented at the IEEE International Electron Devices Meeting (IEDM) on Dec. 15-17. You can get a nice overview on Gizmag.

In order to stack up they had to have a memory that could be manufactured at relatively low temperatures,  a few hundred degrees (present silicon memory involves heating up to 1,000 degrees...). Happily, they had just such a memory available, a Resistive Random Access Memory (RRAM) they have invented last year.

It will still take a few years, I bet, to move this architecture into mass production and it might be that the evolution in alternatives to silicon (like graphene) will hit the market first.  Still it is interesting to see how researchers keep finding new avenues to circumvent obstacles that seemed to block any further progress.

Author - Roberto Saracco

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